Standard
EDIF Translators
Elgris
develops and supports EDIF (Electronic Design Interchange Format)
translators that are used by designers of application-specific integrated
circuits (ASIC), printed circuit boards (PCB), and multi-chip modules
(MCM). These are EDIF standard translators that you can find
on EDA platforms such as Cadence Design Systems, Mentor Graphics, etc. EDIF translators are used for
migration of designs from one EDA platform to another, integration
from various EDA platforms, and archiving into a neutral format,
EDIF.
There
are three EDIF standards to translate electronic designs between
EDA systems currently in use: EDIF V 2 0 0, EDIF V 3 0 0, and EDIF
V 4 0 0. EDIF V 2 0 0 is the most widely used format for schematic
and logical netlist design interchange. EDIF V 3 0 0
is a brand new standard format designed to replace EDIF 2 0 0 for
schematic and logical netlist design interchange. EDIF V 4
0 0 is a superset of EDIF V 3 0 0. In addition to schematic
and logical netlist, EDIF V 4 0 0 includes constructs to handle
PCB and MCM layouts. EDIF V 4 0 0 is well suited for CAD to
CAD or CAD to CAM design interchange: it covers technology and design
rules, can handle MCM descriptions, and allows for the transfer
of documentation associated with physical layouts such as assembly
drawings.

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